GitHub project catalogs worst-case x86 instruction latency, with fxrstor64 stretched to 62 seconds on Ryzen hardware

A public repository called Assembly Hall of Shame explores the opposite of normal performance tuning: finding the slowest possible execution of individual assembly instructions. Its current x86 champion is fxrstor64, which was made to take about 198 billion cycles, or 62 seconds, by forcing a 512-byte state load through heavily contended PCIe MMIO traffic.

The project highlights how instruction latency can explode under pathological hardware and I/O conditions, far beyond what typical CPU optimization guides describe. It is a useful reminder that modern performance depends not just on opcodes, but on system-level interactions across caches, memory, buses, and devices.